1. Cross-Reference to Related Applications
This application is related to:
Application Ser. No. 07/996,278, entitled "Peripheral Component Interconnect Special Cycle Protocol Using Soft Message IDs," filed on same date herewith by T. Heil, and assigned to the assignee of this application;
Application Ser. No. 07/996,277, entitled "Peripheral Component interconnect In Concurrent Architectures And As A Main Memory Bus," filed on same date herewith by T. Heil et al. and assigned to the assignee of this application; and
Application Ser. No. 07/996,276, entitled "Multi-Port Processor With Peripheral Component interconnect Port and RAMBUS Port," filed on same date herewith by T. Heil et al. and assigned to the assignee of this application.
All of the above-identified applications are incorporated by reference herein.
2. Field of the Invention
This invention relates in general to interfaces between computers and input/output (I/O) devices, and in particular to a computer I/O bus.
3. Description of Related Art
A communications interface or input/output bus is typically used in computer systems to interconnect separate devices, such as processors, memories, and peripherals. Standardized interfaces such as the ISA, EISA, or Micro Channel.TM. buses have long been used in computer systems to provide a common I/O board interface across different platforms and different processor generations. However, there are a number of problems associated with these interfaces.
The main problem with these prior interfaces involves cost. Most performance critical peripherals are being moved to motherboards, not only for the performance advantages of processor proximity and minimal interconnect length, but also to leverage the cost and space advantages of higher levels of integration. However, complete integration with the resultant cost and space savings is hampered by lack of a standard component interconnect and the necessity of "glue logic" to connect to the variety of processors and peripheral devices to buses.
Another problem with these prior interfaces involves performance constraints. Standard I/O expansion buses are performance limiting, due to general access latency and the severe bandwidth constraints felt by high performance devices, particularly graphics devices and future communication devices such as fiber LANs.
Further, as highly integrated, performance critical peripheral controllers migrate closer to the processor, there is significant pressure to put them on the "processor treadmill." In other words, these parts are under pressure to track the frequent changes in processor bus frequencies, widths, protocols (e.g., bursting), and signalling standards (e.g., 3 volts). Unnecessarily placing peripheral parts on this treadmill increases system costs and delays the availability of leading edge systems.
Still another problem with prior interfaces involves reliability. As the industry moves toward distributed processing, client systems will become a reliability burden (the weak link) in distributed systems, and therefore will be under pressure to offer levels of reliability and fault containment previously reserved for larger server systems.